For the Verification step, a test is generated to ensure the design outputs meet the design input requirements. If the test doesn’t pass, then a deviation essentially occurs. Has anyone encountered a Verification Test that didn’t pass? If it didn’t pass what was your process for changing the test, changing the DSD, etc?

We tested the spec of a dimension for a subassembly. The spec that was initially decided on was too small and it failed the verification test protocol. We then had to open Change Orders to open up the spec and tolerance and then adjust the verification protocol accordingly and re-run the test.